ChipScope in Verilog Debugging Utility

From Catholicpenguin

Last updated: 1/30/09

Designed for Python 3

'''
This hacky script is used in debugging with ChipScope, where you want to grab
all the signals of a module, like:
    module m(
     .tx_reset(tx_reset_0_i),
     .tx_data(tx_data_0_i),
     .tx_data_valid(tx_data_valid_0_i),
     ...
    );
The pain comes in extracting the internal signals, reversing them so the assign
goes in the order you expect, and then figuring out what the bit width of all
the signals are so you can instatiate a core of the right size. This helps.

-----

Put your module instations in a file, one per line like:
     .tx_reset(tx_reset_0_i),
     .tx_data(tx_data_0_i),
     .tx_data_valid(tx_data_valid_0_i),

Then, call this script with that file, plus the original Verilog source file:
    python grab_signals_for_chipscope.py signals.txt file.v

What you'll get out is a list of the signals in reverse order, for assigning to
a ChipScope trigger:
    tx_data_valid_0_i,
    tx_data_0_i,
    tx_reset_0_i,

plus, the script will search the Verilog file for the definitions of these
signals, print them out (so you can check that it got it right),
and attempt to add up the bit widths:
    wire     [7:0]  tx_data_0_i;
    wire            tx_data_valid_0_i;
    reg             tx_reset_0_i;
    Bits: 10
'''
import re
import sys

try:
    sys.argv[1]
    sys.argv[2]
except:
    print ('Usage: grab_signals_for_chipscope.py signals_to_monitor.txt orig_file.v')
    exit(-1)

# Read signals
data = []
with open(sys.argv[1],'r') as signals:
    for signal in signals:
        data.append(signal)

# Parse and reverse all the signals we want to display
data2 = []
for l in data:
    data2.append( l.split('(')[1].split(')')[0] )

data2.reverse()
print('Signals to monitor in reverse:')
for i in data2: print(i+',')
print('########################################\n\n')

         
# Parse the file and find the widths of all the signals
print('Found these definitions for the above signals:')
started = False
total_bits = 0
with open(sys.argv[2],'r') as f:
    for l in f: 
        l=l.strip()
        if l==');': started = True

        if started:
            for i in data2:
                if (i in l):
                    if 'input' in l or 'output' in l or 'wire' in l or 'reg' in l:
                        bits = 1
                        if '[' in l:
                            m=re.search('\[([0-9])\:([0-9])\]',l)
                            if m:
                                bits = int(m.group(1))+1 - int(m.group(2))
                        print(l)
                        total_bits += bits

print('And in total, the signals are %d bits wide'%total_bits)